1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-114208, May 18, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, chip-on-chip (CoC) type semiconductor devices have received attention, in which through silicon via (TSV) chips are stacked in plurality. Through electrodes are disposed in the TSV chips. Bump electrodes are bonded to each other via through electrodes so that the TSV chips are stacked. However, the bump electrodes have a height of about several micrometers to tens of micrometers. The small height of the bump electrodes can form a narrower gap between the TSV chips than the minimum gap. The minimum gap needs to allow the gap to be sealed with sealing agents without forming a lot of voids. When the semiconductor device is sealed by a molding process, there is a probability of formation of voids in the gap of the TSV chips.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-214220 discloses a method of injecting an underfill from sides of TSV chip stacks in advance to prevent the formation of voids. After the underfill is heated and hardened, the entire surfaces of the TSV chip stacks are overmolded by a mold resin so that the occurrence of voids can be prevented between the TSV chips in overmolding. In addition, as such a molding method, a transfer molding method using a mold having a predetermined size has been disclosed.